Will two FPGAs compile the same code bitstream differently?

Check the pin and package.

Some are down, some are not.

The bitstream is unique to the part, so you must re-synthesize, place and route your code.

The constraints must be revalidated, errors removed, and warnings understood.

This all went well (no problem), but I don't know how well your RTL (verilog or VHDL) is written.

If it is a fully synchronized system, then I expect no problems.

1) This is a lot of decline, but it requires more power.

You should check the PCB design guide to see if you need to add bypass capacitors for new components.

2) Even if you only need to replace with the same XC7A50T-2FTG256I as the original part, the bit stream will be different.

Please note that some Artix-7 parts use the same mold as other parts.

You can easily find these parts by looking at the static power consumption and bit stream length, which are the same for parts using the same chip.

Your original part is actually XC7A50T, and its ID code has been changed so that the tool can enforce restrictions on logic usage.

However, this is not done by eliminating the use of specific resources (for example, preventing the use of certain logical columns).

On the contrary, as long as the total number of resources in the design does not exceed the data sheet number of the XC7A35T, the tool allows you to use any part of the device.

What you get from it is a part that can be filled to almost 100% of the specified capacity, and there are still no problem places and routes.

Therefore, if you are "insufficient" but still within the limits of the data sheet, you may stick to the original parts.

The same is true for parts that allow the use of the entire chip, including XC7A50T and XC7A100T.

When you fill them to about 80%, these parts will start to appear congested.

The speed rating is marked on the device.

It is not enforced by the bitstream.