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ISO7220CDR

DGTL ISO 2500VRMS 2CH GP 8SOIC

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ISO7220CDR

DGTL ISO 2500VRMS 2CH GP 8SOIC

$200 이상 주문 시 한정판 중국 스타일 선물을 받으실 수 있습니다..

$200 이상 주문 시 한정판 중국 스타일 선물을 받으실 수 있습니다..

1000달러 이상 주문 시 배송비 30달러가 면제됩니다..

$5000 이상 주문 시 배송비 및 거래 수수료가 면제됩니다..

이 혜택은 신규 고객과 기존 고객 모두에게 적용되며 2024년 1월 1일부터 2024년 12월 31일까지 유효합니다..

  • 제조업체:

    TI

  • 데이터 시트:

    ISO7220CDR datasheet

  • 패키지/케이스:

    SOP-8

  • 제품 카테고리:

    IC 칩

  • RoHS Status: RoHS 상태 Lead free/RoHS Compliant

지금 견적 요청을 제출하시면 1년 이내에 견적을 제공해 드릴 예정입니다. 5월 06, 2024. 지금 주문하시면 이내에 거래가 완료될 것으로 예상됩니다. 5월 09, 2024. Ps:시간은 GMT+8:00 기준입니다.

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재고:15000 PCS

우리의 약속은 12시간 이내에 신속한 견적을 제공하는 것입니다. 추가 지원이 필요하시면 다음 주소로 문의해 주세요. sales@censtry.com.

ISO7220CDR 제품 세부 정보

FEATURES

• 1, 25, and 150-Mbps Signaling Rate Options

– Low Channel-to-Channel Output Skew; 1 ns max

– Low Pulse-Width Distortion (PWD); 1 ns max

– Low Jitter Content; 1 ns Typ at 150 Mbps

• Typical 25-Year Life at Rated Voltage (see app. note SLLA197 and Figure 19) 

• 4000-Vpeak Isolation, 560 V peak VIORM

– UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2), IEC 61010-1

– 50 kV/μs Typical Transient Immunity

• Operates with 3.3-V or 5-V Supplies

• 4 kV ESD Protection

• High Electromagnetic Immunity

• –40°C to 125°C Operating Range


APPLICATIONS

• Industrial Fieldbus

– Modbus

– Profibus™ – DeviceNet™ Data Buses

• Computer Peripheral Interface

• Servo Control Interface

• Data Acquisition


DESCRIPTION

The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are oriented in the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic input and output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to 4000 V. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, and prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry.

A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received every 4 μs, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.

The small capacitance and resulting time constant provide very fast operation with signaling rates available from 0 Mbps (DC) to 150 Mbps.(1)The A- and C-option devices have TTL input thresholds and a noise filter at the input that prevents transient pulses from being passed to the output of the device. The M-option devices have CMOS Vcc/2 input thresholds and do not have the input noise-filter and the additional propagation delay.

These devices require two supply voltages of 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when supplied from a 3.3-V supply and all outputs are 4-mA CMOS.

These devices are characterized for operation over the ambient temperature range of –40°C to 125°C.

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