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TLC555QDR

IC OSC SGL TIMER 2.1MHZ 8-SOIC

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TLC555QDR

IC OSC SGL TIMER 2.1MHZ 8-SOIC

$200 이상 주문 시 한정판 중국 스타일 선물을 받으실 수 있습니다..

$200 이상 주문 시 한정판 중국 스타일 선물을 받으실 수 있습니다..

1000달러 이상 주문 시 배송비 30달러가 면제됩니다..

$5000 이상 주문 시 배송비 및 거래 수수료가 면제됩니다..

이 혜택은 신규 고객과 기존 고객 모두에게 적용되며 2024년 1월 1일부터 2024년 12월 31일까지 유효합니다..

  • 제조업체:

    TI

  • 데이터 시트:

    TLC555QDR datasheet

  • 패키지/케이스:

    SOP-8

  • 제품 카테고리:

    IC 칩

  • RoHS Status: RoHS 상태 Lead free/RoHS Compliant

지금 견적 요청을 제출하시면 1년 이내에 견적을 제공해 드릴 예정입니다. 5월 03, 2024. 지금 주문하시면 이내에 거래가 완료될 것으로 예상됩니다. 5월 08, 2024. Ps:시간은 GMT+8:00 기준입니다.

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재고:65000 PCS

우리의 약속은 12시간 이내에 신속한 견적을 제공하는 것입니다. 추가 지원이 필요하시면 다음 주소로 문의해 주세요. sales@censtry.com.

TLC555QDR 제품 세부 정보



  • Very Low Power Consumption

− 1 mW Typ at VDD = 5 V

  • Capable of Operation in Astable Mode

  • CMOS Output Capable of Swinging Rail to Rail

  • High Output-Current Capability

    − Sink 100 mA Typ

    − Source 10 mA Typ

  • Output Fully Compatible With CMOS, TTL,and MOS

  • Low Supply Current Reduces Spikes

  • During Output Transitions

  • Single-Supply Operation From 2 V to 15 V

  • Functionally Interchangeable With the

  • NE555; Has Same Pinout

  • ESD Protection Exceeds 2000 V Per

  • MIL-STD-883C, Method 3015.2

  • Available in Q-Temp Automotive 

  • High Reliability Automotive Applications

    Configuration Control/Print Support

    Qualification to Automotive Standards

description

The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS process. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering. While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC555 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555.


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